The present invention relates to radio communications systems for transmitting and receiving coded digital information, and more particularly to digital cellular radio telephone systems and interference cancellation between radios using the same channel frequency.
One problem that occurs in mobile communications systems, such as in cellular telephone systems, is co-channel interference that is created when two or more transmitters (such as mobile units) simultaneously modulate different symbols onto the same carrier frequency. This situation is illustrated in FIG. 1, which is a block diagram of a communications system in which at least two transmitters 1, 2 transmit data on the same frequency. Each of the transmitters 1, 2 may intend for its data to be received by a different one of, say, two receiver sites 3, 4. However, the data from each of the transmitters 1, 2 may all be received at the same receiver site (e.g., a first receiver 3) with consequent co-channel interference between the signals.
The transmitters 1 and 2 are conventional transmitters, such as those utilized in digital cellular radio telephones conforming to standards such as GSM, IS136 or IS54. FIG. 2 is a block diagram of an exemplary one of these transmitters. The exemplary transmitter comprises an information source 10 that provides an information bit stream to an error correction encoder 11. The information source 10 may, for example, be a speech digitizing and compression device. The error correction encoder 11 is preferably a convolutional encoder comprising a register 111 through which the information bits are clocked, and a parity bit computer 112 connected to taps on the register 111. The parity bit computer 112 forms coded bits or parity bits which are a function of selected register bits. The number of parity bits formed on each shift is equal to the reciprocal of the coding rate, r. The parity bits supplied by the encoder 11 are fed to an interleaver 12. The interleaver 12 re-orders the output parity bit sequence from the encoder 11 to produce the sequence for transmission. While the encoder 11 is not necessarily the same for each of the transmitters 1 and 2, each interleaver 12 in the system may perform identical interleaving such that corresponding bits from different transmitters 1, 2 are transmitted at the same time. The interleaver incorporates the function of interspersing a known symbol pattern into the transmitted stream for the purposes of receiver synchronization and for providing a vector reference to the receiver 3, 4 for processing unknown symbols.
Before or after interleaving, or both, scrambling or encryption of the coded or uncoded information symbols takes place by utilizing either or both of first and second combiners 17 and 18 to combine bits with keystream bits generated by a key generator 16. The key generator 16 generates the key stream in dependence on key bits that are at least known to the receiver for every transmitted signal that the receiver is intended to demodulate. The key stream may otherwise be kept secret from potential eavesdroppers.
The enciphered bit sequence for transmission is modulated using a radio frequency modulator 13 to produce a drive signal for a transmitter 14. The transmitter 14 may then further condition the signal by, for example, upconverting it to a desired radio frequency channel and amplifying it to a transmit power level. The further conditioned signal is then supplied to an antenna 15 for transmission.
In order to mitigate this type of co-channel interference, it is known to perform joint demodulation of these overlapped signals by simultaneously hypothesizing symbols transmitted by at least a first and a second transmitter. An example of such a scheme, applied in connection with antenna arrays, is disclosed in U.S. Pat. No. 5,619,503 (Dent, filed Nov. 1, 1994), which is hereby incorporated by reference herein in its entirety.
Joint demodulation of multiple signals transmitted on different frequencies in order to mitigate adjacent channel interference is furthermore disclosed in U.S. patent application Ser. No. 08/393,809 (Dent, filed Feb. 24, 1995), which is hereby incorporated by reference herein in its entirety. This referenced application shows that a Maximum Likelihood Sequence Estimator (MLSE) is capable of operating sequentially to decode one bit transmitted at the same instant in time from each of a number of transmitters using sequential frequencies, as opposed to prior known MLSE which decoded bits transmitted at the same frequency sequentially in time.
U.S. Pat. No. 5,230,003 (Dent and Raith, issued on Jul. 20, 1993), which is hereby incorporated by reference herein in its entirety, also describes distinguishing between two differently coded signals. However, this patent is concerned with distinguishing between signals that may be alternatively transmitted; it is not concerned with distinguishing between signals that are simultaneously transmitted.
U.S. Pat. No. 5,673,291 (Dent, filed Sep. 14, 1994), which is hereby incorporated by reference herein in its entirety, discloses the simultaneous demodulation and error-correction decoding of a signal using a single MLSE process. Joint demodulation and decoding, referred to as "decodulation", can improve performance over that of separately demodulating then decoding a signal, because the output of the demodulation process in the latter case is not constrained to be a valid codeword, and thus errors occur at the demodulation stage. In the decodulation process, however, only signals corresponding to valid codewords are demodulated, thereby avoiding errors at the demodulation stage. FIG. 3 illustrates the internal arrangement of an implementation of a decodulator for simultaneously demodulating and error-correction decoding a single signal according to the above-incorporated U.S. Pat. No. 5,673,291. Of particular importance is the column of complex arrays marked Z0 to Z15 and entitled "reference vector arrays." Each quantity Z is preferably a multiplicity of complex values, that is, a complex vector array, with each value in each array Z representing the best current estimate of the radio signal vector just prior to a signal sample to be processed, under the assumption that the associated "current hypothesis" is true. The number of values in each array Z is preferably equal to twice the number of known symbol blocks included in the signal bursts being processed, in the case of differential modulation, or equal to the number of known symbol blocks in the case of absolute phase modulation. The number of values is preferably equal to twice the number of known symbol blocks also for absolute (coherent) modulation, when the propagation path suffers from fast fading. For example, if interleaving spreads differentially coded symbols over two signal segments or bursts, such as time division multiple access (TDMA) bursts or data packets, interspersed with six known, isolated sync symbols per burst, then the number of values in each array Z such as Z0 is 24. In this example, there are six known symbol blocks, but each consists only of a single, isolated symbol. The number of known symbols in a block may, however, be greater than one. The values represent estimates of the signal vector Z.sub.L at a position to the left and Z.sub.R to the right of a known sync symbol respectively. The Z values are initialized to estimates of the nominal complex reference value for the signal on each side of the respective sync symbol. For example, if the first sync symbol in the first signal burst is known to be differential rotation through +90 degrees, and the received signal vectors before and after this known rotation are respectively Z(i-1) and Z(i), then the best estimate of the phase to the left of (i.e., before) the sync symbol is given by Z.sub.L =(Z(i-1)-jZ(i))/2, and the best estimate of the signal vector to the right of (i.e., after) the sync symbol is Z.sub.R =(jZ(i-1)+Z(i))/2.
The former is obtained by rotating Z(i) backwards through the known 90 degree phase shift to align it with the previous value Z(i-1), and then averaging the two. The latter is obtained by rotating Z(i-1) forward through the known 90 degree phase shift to align it with Z(i) and then averaging the two. A variable scaling of the sum other than by division always by two is sometimes beneficial as disclosed in the incorporated application.
Decodulation proceeds as follows. A hypothesis for a transmitted symbol sequence filling all positions in the convolutional encoding shift register 111 is made. For example, if a constraint-length 5 code is employed, the encoding shift register has five stages. Selecting the row in FIG. 3 corresponding to the hypothesis 0000 and hypothesizing a new 0 bit is equivalent to hypothesizing that the transmitting encoder register 111 contained five zeros at that point. These hypothesized shift register contents are then used to generate the encoded bits P1, P2, . . . that should have been transmitted if the hypothesis is correct. This is carried out by incorporating into the receiver a transmitter model 60 that includes a model of the convolutional encoder 11. The transmitter model 60 also incorporates the known modulation parameters so that complex signal values representative of P1 and P2 can be predicted, as well as the interleaving or bit placement information to predict where in the received signal segments the encoded bits P1, P2, . . . would be expected to be observed.
The first bits P1, P2 hypothesized with the aid of the transmitter model 60 are preferably located adjacent to known sync symbols as disclosed in the referenced patent application. Assuming binary modulation such as Minimum Shift Keying (MSK), in which a binary `1` is represented by a +90 degree phase rotation from one sample to the next and a binary `0` is represented by a -90 degree rotation, then if P1 is hypothesized to be a `1` we should receive a signal sample rotated by +90 degrees relative to the reference vector (a Z.sub.R or Z.sub.L value) that the signal sample lies adjacent to. Thus the relevant reference value is extracted from the array Z0 (a Z.sub.R or Z.sub.L value dependent on whether the signal sample being processed lies to the left or the right of a known symbol block) and rotated by 90 degrees before comparison in comparator 61 with the received sample. This corresponds to the hypothesis that P.sub.1 is a zero. The error is squared to produce the signal mismatch value for P.sub.1 which is added to the cumulative path metric for the state 0000 in adder 62. This is repeated for P.sub.2 or any other coded bits, the number of which is the reciprocal of the coding rate r, with each received signal sample corresponding to a coded bit being selected from a position in the received sample stream according to the known interleaving pattern. According to whether this position is to the left or to the right of any known sync symbol block, it is compared with the relevant Z.sub.L or Z.sub.R value from the array Z0.
The new path metric is, at this point, only regarded as a candidate value for a new state/hypothesis 0000, as the hypothesis 1000 followed by a new bit 0 is an equally possible candidate. When the convolutional encoder shifts its encoding register one place to the left, the leftmost 1 or 0 will move out of the register leaving, in both cases, 0000 in the four leftmost positions. Thus, a candidate metric is calculated in precisely the same way as above, but starting with the hypothesis 1000-0 and using its corresponding reference vector Z-values. The second candidate metric from a second adder 64 is then compared with the first from the first adder 62 in a second comparator 63 and the lower of the two is selected. If this is from the second adder 64, then the hypothesis 1000-0 is deemed to be a better hypothesis than 0000-0, and state/hypothesis 1000 is called the "best predecessor" to new state 0000. The contents of the "already processed" memory associated with the best predecessor are then selected to be the contents of the already processed symbol memory of new state 0000, and a `1` or a `0` is left-shifted in from the right hand side of this memory according to whether the best predecessor was 1000 or 0000. To the left of FIG. 3, there is an area of memory labeled "ALREADY PROCESSED SYMBOL HYPOTHESES." This is sometimes also known more succinctly as the "PATH HISTORY." If 1000 is deemed the "best predecessor state," then its path history is used as the path history for new state 0000, else the path history of old state 0000 is used. If the former, its path history, 11011011, is left shifted with the state number 1000 and the new bit=0 so that 11011011-1000-0 becomes 110110111-0000, where the "110110111" part is the new path history, and the "0000" part is the new state number. If 1000 is not deemed the "best predecessor state," so that the path history of old state 0000 is used, then 10010011-0000-0 becomes 100100110-0000, where the "100100110" part is the new path history, and the "0000" part is the new state number. The lower of the candidate metrics also becomes the new path metric, and the reference vector array associated with the best predecessor is selected to be the reference vector array for the new state, after updating it preferably using a Kalman channel tracking algorithm per state.
Repeating the above process for a new bit hypothesis of `1` instead of `0` generates a new state 0001 in the same manner. Starting with, in turn, pairs of hypotheses 0001-1001, 0010-1010, and so on, and repeating the above for each pair then generates the rest of the new states so that there are, at the end of one iteration, the same number of new states (sixteen in this example) as at the beginning.
The above procedure is used to process sequentially the received samples in a preferred order in which unknown symbols lying next to known or already decoded symbols are processed first.
The previously referenced U.S. Pat. No. 5,673,291 discloses the use of decodulation for the purpose of discriminating a wanted signal from noise and interference. This reference is silent, however, with respect to techniques for separating two or more wanted signals from each other as well as from noise and interference.
U.S. Pat. No. 5,764,646, entitled "Packet Data Transmission With Clash Subtraction" (Dent, filed Apr. 2, 1996, and bearing Attorney Docket No. 027545-142), which is hereby incorporated by reference herein in its entirety, describes a packet data receiver for receiving bursts of coded data. The invention disclosed therein has means for detecting when a data burst or packet is at least partially overlapped by an interfering packet. The interfering packet, if stronger, is first decoded and subtracted from the received signal before resuming decoding of the received packet. In this case, joint decoding is not used because the overlapping packets are assumed to be very asynchronous, that is, not time-aligned.